The invention relates generally to over voltage protection circuits for protecting other circuits from higher than desired voltage levels, and more particularly to voltage scaling circuits for protecting an input to a protected circuit.
With the continued demand for higher speed and lower power consumption integrated circuits a need exists for simple, low cost and reliable over voltage protection circuits. For example, CMOS based video graphics chips with 128 input/output ports (I/O) ports are required to operate at clock speeds of 125 MHz to 250 MHz. Such devices may use a 2.5 V power supply for much of its logic to reduce power consumption. One way to increase the operating speed of such devices is to decrease the gate length of core circuitry transistors. However, a decrease in the gate length of MOS devices can reduce the gate breakdown voltage to lower levels. For example, where an integrated circuit contains digital circuitry that operates from a 2.5 V source and is fabricated using silicon dioxide gate widths of 50 Angstroms, a resulting gate breakdown voltage may be approximately 3.5 volts. Such IC's must often connect with more conventional digital devices that operate at 5 V or 3.3 V. A problem arises when the core logic circuitry (operating at 2.5 volts) receives 5 V digital input signals from peripheral devices on input pins. Such standard 5 V input signals or 3.3 V input signals can cause breakdown damage if suitable voltage protection is not incorporated.
FIG. 1 shows a known over voltage protection arrangement that attempts to overcome this problem. As seen, a resistor R is placed in the input path from an input pin P to the input I of a MOS based core logic stage, such as an input/output port on a CPU or other processing unit. A clamping diode D is placed across the input I of the core logic stage and is connected to a 2.5 V supply voltage used by the core logic to clamp over voltages coming from pin P. In operation, resistor R restricts current flow to the core logic circuit and a voltage drop occurs across the resistor. When an input voltage is high enough to cause the diode D to conduct, the diode clamps the input voltage to a fixed level (2.5 V+diode junction voltage drop). Several problems arise with such a configuration. If the core logic is fabricated with gate widths of 50 angstroms, a breakdown voltage of only 3.5 volts is required to damage the core logic stage (0.7V/A*50a=3.5 V). With the diode drop of approximately 7 volts, a 3.2 V input voltage is a maximum input voltage to the core logic stage, however this is very close to the 3.5 V breakdown voltage so that over temperature and time, circuit reliability may be compromised. Also, the clamp diode D allows additional current to flow through the substrate which can cause latch-up of core logic circuitry.
Another problem is the use of resistor R. Such resistive elements take up large areas on integrated circuits and dissipate large amounts of power, hence heat, when an input voltage such as 5 volts is placed on pin P. In addition, a large time delay can occur due to the resistor R and the parasitic capacitance of the gate junction of the core logic circuit. This time delay reduces the speed of operation of the system.
Consequently there exists a need for a protection circuit that reduces power consumption, improves the speed of operation of a system in a simple and reliable manner. It would desirable if the protection circuit provided voltage scaling in a cost effective manner.